Debugging, C, Shell, Tcl, Verilog, System Verilog, Python, Perl, directed and constrained random methodologies, UVM methodology, Metric Driven Verification, functional and code coverage, assertions, formal verification methodologies

Vcs, Tcl, Verilog, System Verilog, Python, Perl, Sec, Questa, spyglass, LINT, Xcelium, cdc, Jasper-FPV, Questa CDC, RDC

UNIX, Verilog, Debugging, design quality checks, SoC connectivity concepts, Simulation, RTL integration, Digital Design, Windows environments, systemverilog, RTL Coding, Ms Office Tools, ASIC SoC design methodologies

C, Git, Shell, Perl, Python, Tcl, Xilinx FPGA, Siemens Veloce, Cadence Zebu, Palladium, Uvm, systemverilog, Vivado, SVA