C, C++, Ethernet Switching, Uart, Spi, Verilog, Python, Tcl, systemverilog, Pre-silicon system validation, TSN, Packet processing, FPGA emulation, I²C, MACsec, Microcontroller-based subsystems

Vcs, Makefile, Shell, Perl, Python, System Verilog, Assertion-based verification, Xcelium, UVM methodology, Constrained-random verification, Questa, Vivado Simulator, formal verification

C, coverage closure, microprocessor ISA, coverage planning, Data-Consistency verification, power management verification, testbench development, clocking reset power-up sequences, low power verification flows, systemverilog

data engineering , Java, Maven, New Relic, Devops, Software Engineering, Gradle, Gcp, Docker, Terraform, ECS, Data Engineer, Kubernetes, Python, AWS, Streaming Data, Braze, CI CD, mParticle, Confluent Kafka, Cloud Run, OpenTelemetry

Tcl Scripting, Pcie, Soc Architecture, Python, Axi, formal verification, regression management, BUS Protocols, simulation coverage analysis, Uvm, systemverilog

code coverage , C, Shell, Verilog, Debugging, Flash, Python, System Verilog, Perl, Tcl, interconnect, Memory, UVM methodology, Microprocessor architecture, clocking system modes, power management, SoC Verification, constrained random methodologies, Metric Driven Verification, Rom, formal verification methodologies, Axi, MRAM, AHB, Ram

Shell, Version Control Systems, Scripting, System Verilog, Python, Soc Architecture, Perl, performance features, functional and code coverage methodologies, Advanced SystemVerilog, X86 based SOC DV, Uvm, coverage closure, Security, BFMs, UVCs, power management, regression automation, memory subsystems, Debug, interconnects, SoC IP verification environments, Asic Design Verification, debugging skills, SoC verification methodologies, simulation and verification tools, VIPs