C, Vcs, Perl, Verilog, spyglass, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, EVE, Veloce, ASIC Design, formal verification

multi-domain clock synchronization, spyglass, Verilog RTL coding, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, high performance memory subsystems, ASIC debugging

Fcoe, Ethernet, spyglass, Verilog RTL coding, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, multi-domain clock synchronization, high performance memory subsystems, ASIC debugging

code coverage , Verilog, System Verilog, LINT, cdc, AXI protocol, Low power synthesis, Formality, SoC level Synthesis, UPF, Rtl Design, Synthesis, AMBA, Timing Analysis, RTL Coding, AHB, ip development, functional coverage, front-end design tools

Uart, Spi, Verilog, I2c, LINT, cdc, MAS development, Sub-system design, SoC integration, ip design, Quality check flows, AMBA bus protocols, Axi, APB, RTL Coding, Medium complexity protocol, AHB, Microarchitecture