static timing analysis, Synthesis, RISC CPU IP, ARM CPUs, Emulation, chip validation, Timing Analysis, CPU microarchitecture, SoC design methodology, Physical Design, IP integration, CDC analysis, Rtl Design, Floor Planning, linting, BUS Protocols, Timing Closure, characterisation, silicon bring-up, Verification, equivalence checking

Java, Networking, Cloud Security, Sql, Nosql, Cloud Computing, Gcp, Apache Kafka, Python, Kubernetes, AWS, Ai, GCP Pub Sub

Verilog, Integration, System Verilog, ATB-AMBA protocol, SoC development, Uvm, Debug architecture, Gate Level simulations, verification testbench, Axi, ASIC Design, Power aware simulations, Verification, Validation, AHB

Perl, Python, Tcl, Logic Synthesis, Physical-Aware Synthesis, PPA optimization, UPF management, Low-Power Implementation, systemverilog

Perl, Python, Tcl, UPF, power simulation on VCS, UVM Test Bench development

Fcoe, spyglass, Verilog RTL coding, Synopsys Design Compiler, ASIC debugging, Multi-domain clock synchronization, High performance memory subsystems, High-speed serial interfaces, LEC, Networking protocols Ethernet, Verplex

Static timing analysis, Linux, Lsf, Bitbucket, Git, Unix, Splunk, AI ML, Python, Jenkins, EDA Tools, convolutional Networks, make, GenAI, SW development, CI CD process, Implementation, design layout constraints, DesignSync, debug tools, Power-aware flows, UPF, Clocks, Design Verification, cdc, reinforcement learning, Graph Neural Networks, SDC, Dft, RDC