synplify pro , Verilog, Ise, Synthesis, VHDL, logic simulation, Modelsim, altera quartus, Xilinx Vivado

rtl verification , Bash, Perl, Verilog, Python, Tcl, FPGA Bring-up, Hardware Validation, systemverilog, FPGA RTL Design, RTL Simulation, FPGA Debugging, ASIC Design, SoC Integration

System Verilog, Synthesis tools of Synplicity Synplify, Development tools including Xilinx ISE, Simulation tools of ModelSim SE, Verilog Hdl, Hardware description language VHDL, Solid Verilog RTL and test bench coding skills, FPGA design processes, altera quartus, Familiar with at least one mainstream FPGA and development platform Xilinx Altera Lattice