static timing analysis, Synthesis, RISC CPU IP, ARM CPUs, Emulation, chip validation, Timing Analysis, CPU microarchitecture, SoC design methodology, Physical Design, IP integration, CDC analysis, Rtl Design, Floor Planning, linting, BUS Protocols, Timing Closure, characterisation, silicon bring-up, Verification, equivalence checking

Perl, Python, Tcl, Timing Closure STA, RTL-to-GDSII Execution, Red Hawk, Programming Scripting, Fusion Compiler, LEC, Tempus, Cross-Functional Collaboration, Physical Formal Verification, Innovus, Calibre, primetime, PPA Optimization, EDA Tools, VCLP

Verilog, Integration, System Verilog, ATB-AMBA protocol, SoC development, Uvm, Debug architecture, Gate Level simulations, verification testbench, Axi, ASIC Design, Power aware simulations, Verification, Validation, AHB

bist , C, Vcs, Verilog, Python, Asic verification, Genus Design Compiler, digital timing constraints, XCelium, high-speed SerDes, SOC interconnect fabrics, ASIC tool flows, Scan Insertion, DFT methodologies, Timing Analysis, systemverilog, FPGAs, ASIC synthesis, Axi, AMBA, Timing Constraints, ATPG, APB, Questa, microcontroller platforms, Cadence Virtuoso, AHB

.NET, .Net Core, C#, Graphql, Kafka, Css3, Angular, Automated Testing, Git, Typescript, Javascript, Gcp, Docker, Html5, ASP.NET, Distributed Systems, Azure, Kubernetes, AWS, NoSQL databases, Microservices architecture, CI/CD pipelines, Service Bus

Software Design, Java, Web Services, Database Design, C, Objective-c, Distributed Systems, Ruby, Python, Sql

arm architecture , Uart, Verilog, I2c, Pcie, Flash, digital ASIC design, system memory hierarchy, AMBA bus protocols, constraints development, systemverilog, low power methodology, system debug infrastructure, multi-core SOC designs, DC DC-T based synthesis, RTL level checks, DRAM, ARM v8 and v9 specifications, SSP, ARM based ecosystem components