Hierarchical design implementation, Feed-through planning, PnR implementation, PV clean-up, SoC Full-chip floorplanning, PG creation and push-down methodologies, Scripting flow deployment, Physical Verification, RDL knowledge, Sta, Die file generation

power integrity , Perl, Python, Tcl, Sta, primetime, Cadence Innovus, Tempus, EM IR analysis, Voltus

production readiness , power analysis, Design Reviews, Silicon Bring-up, PnR Implementation, Verification, Physical Design, Placement, Floor Planning, ASIC Design, Low Power Verification, Rtl Design

Logic Design, Physical design architecture, P R Timing and Physical verification tools, floorplanning, Physical implementation flows, Physical design flows

Synthesis, physical verification closure, Formal, Timing Closure, block chip level implementation from Netlist to GDS, scripting skills – TCL

Python Scripting, Verilog, Physical Design, VHDL, Timing verification and signoff, Low Power Checks, Physical Verification

Python, Tcl, Sta, IR drop, physical sign-off, CTS, primetime, floorplanning, Cadence Innovus, Tempus, LVS, PNR, DRC, static power optimization, Synopsys ICC2

power optimization , FPGA Design, floorplanning, Place And Route, Timing Analysis, DRC/LVS Checks, Signal Integrity, Physical Verification, RTL Synthesis, Circuit Layout

Python Scripting, Verilog, Physical Design, VHDL, Timing verification and signoff, Low Power Checks, Physical Verification