Usb, Tcl, Verilog, Arm, System Verilog, Ethernet, Perl, Spi, I2c, Python, Soc Architecture, ASIC design flow, Synthesis, LINT, peripheral IPs, Low-power design, Timing Analysis, Axi, BUS Protocols, MBIST, MIPS, Bus Matrix design, AMBA, Rtl Design, Timing constraint SDC, DFT concepts, Power estimations, RDC, Formal CDC

Test Planning, C, Systemc, Shell, Verilog, Tcl, Python, power-aware verification using UPF, systemverilog, NoC bus and interconnect verification, assertions, transaction-level modeling, UVM-based testbench development, constrained-random verification, formal verification

C, Clearcase, Cryptography, Aes, Encryption, Clearquest, Perl, Verilog, Python, System Verilog, LINT, cdc, RTL design using Verilog, hash functions, GMAC, signatures, LEC, SHA, private key, ASIC development tools, random number generator

bandgap references , Dll, DDR, Verilog, Power delivery network, LPDDR, Delays, Oscillators, EM IR simulation, FINESIM, V2I converters, CMOS Amplifiers, Parasitic modeling, charge pumps, LDOs, Hspice, IO circuits, Comparators, Complex Analog Mixed Circuits, Process and temperature sensors