Job Details

Job Description:

Altera's Software, IP and Solutions (SIPS) organization develops configurable intellectual property and embedded solutions that enable customers to use the capabilities of Altera FPGA devices efficiently and reliably. We are looking for an Embedded Systems and IP Engineer to take technical ownership of assigned features or substantial components across design and design verification (DV), from requirements and implementation through validation, documentation, and release.

The ideal candidate possesses strong embedded-systems knowledge with hands-on RTL design and verification expertise. You will work across hardware, firmware, drivers, software, and customer-use-case boundaries to deliver high-quality soft IP and embedded solutions. The role requires sound technical judgment, systematic problem-solving, and the ability to coordinate execution across teams and sites.

Key Responsibilities

Design and architecture

Translate system, product, and customer-use-case requirements into detailed design inputs, interface definitions, and acceptance criteria; contribute to architecture proposals with guidance from senior engineers.
Design, implement, integrate, and debug synthesizable RTL using Verilog and SystemVerilog for FPGA soft IP and embedded systems.
Develop and maintain associated collateral, including register descriptions, constraints, integration guidance, simulation models, design examples, and technical documentation.
Integrate and configure IP and subsystems using Quartus, Platform Designer, Visual Designer Studio, or equivalent FPGA design flows.
Consider area, timing, throughput, latency, power, clocking, reset, CDC/RDC, resource utilization, and maintainability trade-offs; identify and escalate technical risks early.
Support embedded-system bring-up and debug across the FPGA fabric, HPS/Nios V, firmware, drivers, board interfaces, and customer applications.

Design verification and validation

Develop and execute verification plans for assigned IP(s) or embedded-system features, covering unit, subsystem, system, and board-level behavior as appropriate.
Develop or enhance SystemVerilog test benches, UVM or non-UVM environments, drivers, monitors, scoreboards, BFMs, assertions, functional coverage, and directed or constrained-random tests.
Execute simulations, regressions, lint, CDC/RDC, synthesis, timing analysis, and other quality checks; identify coverage gaps and implement or propose closure actions.
Analyze logs, waveforms, traces, and hardware observations to reproduce and root-cause failures across RTL, IP integration, firmware, software, and tools.
Participate in defect triage, communicate verification status and risks, and drive issues in the assigned area to closure with design, architecture, firmware, validation, and CAD-flow partners.
Create and execute negative, corner-case, configuration, interoperability, stress, and end-to-end customer-use-case tests based on the verification plan.

Delivery, automation, and quality

Drive assigned feature or subsystem deliverables through design reviews, implementation, verification, and release milestones.
Develop reusable scripts and automation for verification and development productivity, including regression orchestration, result reporting, and flow improvements.
Identify quality or execution issues and propose process, tool, or methodology improvements that benefit the immediate team and project.

Technical leadership and collaboration

Act as a technical owner for assigned features or components and coordinate dependencies with partner engineers.
Provide technical guidance to junior engineers and interns through reviews, debug collaboration, and knowledge sharing.
Communicate status, risks, and technical trade-offs across geographically distributed teams and collaborate to meet delivery commitments.

Qualifications

Bachelor's, Master's or PhD in Electrical Engineering, Computer Engineering, Electronics Engineering, or a related field.
Typically 5 or more years of relevant experience in embedded systems, FPGA, RTL design, design verification, or a closely related engineering field; equivalent demonstrated expertise may be considered.
Strong practical understanding of digital design, computer architecture, embedded systems, FPGA architecture, and hardware/software interaction.
Experience developing or maintaining verification environments and test content using SystemVerilog, UVM or equivalent methodologies.
Experience with functional coverage, assertions, regression management, waveform analysis, and systematic failure triage.
Proficiency in Python and/or other scripting languages; working knowledge of C or C++ for embedded or verification use cases.
Experience with FPGA implementation and analysis flows, including Quartus or an equivalent FPGA toolchain.
Strong analytical, problem-solving, written, verbal, and cross-functional collaboration skills, with the ability to work independently on complex engineering problems.

Job Type

Regular

Shift

Shift 1 (Malaysia)

Primary Location:

Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.