Job Details:

Job Description:

Altera's Software, IP and Solutions (SIPS) organization develops configurable intellectual property and embedded solutions that enable customers to use the capabilities of Altera FPGA devices efficiently and reliably.

We are looking for an Embedded Systems and IP Engineer to own features and subsystems across design and design verification (DV), from requirements and architecture through implementation, validation, documentation, and release.

The ideal candidate possesses strong embedded-systems knowledge with hands-on RTL design and verification expertise.

You will work across hardware, firmware, drivers, software, and customer-use-case boundaries to deliver production-quality soft IP and embedded solutions. The role requires independent technical judgment, proactive risk management, and the ability to influence execution across teams and sites.

Key Responsibilities

Design and architecture

Translate system, product, and customer-use-case requirements into clear architecture proposals, technical specifications, interface definitions, and acceptance criteria.
Design, implement, integrate, and debug synthesizable RTL using Verilog and SystemVerilog for FPGA soft IP and embedded systems.
Develop and maintain associated collateral, including register descriptions, constraints, integration guidance, simulation models, design examples, and technical documentation.
Integrate and configure IP and subsystems using Quartus, Platform Designer, Visual Designer Studio, or equivalent FPGA design flows.
Account for area, timing, throughput, latency, power, clocking, reset, CDC/RDC, resource utilization, and maintainability trade-offs.
Support embedded-system bring-up and debug across the FPGA fabric, HPS/Nios V, firmware, drivers, board interfaces, and customer applications.

Design verification and validation

Own the verification strategy and plan for assigned IP(s) or embedded-system features, covering unit, subsystem, system, and board-level behavior as appropriate.
Develop or enhance System Verilog test benches, UVM or non-UVM environments, drivers, monitors, scoreboards, BFMs, assertions, functional coverage, and directed or constrained-random tests.
Execute simulations, regressions, lint, CDC/RDC, synthesis, timing analysis, and other quality checks; identify coverage gaps and drive closure.
Analyze logs, waveforms, traces, and hardware observations to reproduce and root-cause failures across RTL, IP integration, firmware, software, and tools.
Lead defect triage, communicate verification status and risks, and drive issues to closure with design, architecture, firmware, validation, and CAD-flow partners.
Define negative, corner-case, configuration, interoperability, stress, and end-to-end customer-use-case tests for robust product behavior.

Delivery, automation, and quality

Lead execution of an assigned feature or subsystem through design reviews, implementation, verification, release readiness, and post-release support.
Improve verification and development productivity through reusable scripts, automation, CI/CD, regression orchestration, result reporting, and flow enhancements.
Identify systemic quality or execution issues and recommend process, tool, or methodology improvements that benefit the wider team.

Technical leadership and collaboration

Serve as a technical lead or feature owner for complex work with multiple engineering dependencies.
Mentor junior engineers and interns through technical guidance, design reviews, debug collaboration, and knowledge sharing.
Communicate crisply across geographically distributed teams, escalate risks early, and build alignment on technical trade-offs and delivery commitments.

Qualifications

Bachelor's, Master's or PhD in Electrical Engineering, Computer Engineering, Electronics Engineering, or a related field.
7 or more years of relevant experience in embedded systems, FPGA, RTL design, design verification, or a closely related engineering field; equivalent demonstrated expertise may be considered.
Strong understanding of digital design, computer architecture, embedded systems, FPGA architecture, and hardware/software interaction.
Experience creating or maintaining verification environments and test content using System Verilog, UVM or equivalent methodologies.
Experience with functional coverage, assertions, regression management, waveform analysis, and systematic failure triage.
Proficiency in Python and/or other scripting languages; working knowledge of C or C++ for embedded or verification use cases.
Experience with FPGA implementation and analysis flows, including Quartus or an equivalent FPGA toolchain.
Strong analytical, problem-solving, written, verbal, and cross-functional collaboration skills.

Qualifications:

Job Type:

Regular

Shift:

Shift 1 (Malaysia)

Primary Location:

Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.