Design Verification Engineer
Design Verification Engineer
DIGICOMM Semiconductor- Posted a day ago
- Be among the first 10 applicants
Job Description
Attention Design Verification Engineers ! Elevate your career to new horizons ! Your quest concludes here – embrace the chance to embark on a transformative journey with Digicomm Semiconductor Private Limited as your next professional milestone.
Responsibilities
- Hands On Experience, in IP/SOC Verification
- Have Experience of one or more Project Cycles including Tape Outs
- Design & Verification Failure Debugging Skills
- Verilog, System Verilog, & UVM Testbench Coding
- Functional Coverage Development, & Coverage Closure
- Assertion/Checker Development
- Testcase Planning & Development
- Practical Knowledge of Protocols like: PCIe, Ethernet, CXL, USB, CAN, LIN, FlexRay, AXI, AHB, APB
- Concepts in Digital Design
- Problem Solving & Analytical Skills
Qualifications : BTECH/MTECH
- Experience : The Engineers with 2 to 8 years of Experience
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
Assertion Checker Development
Coverage Closure
Functional Coverage Development
Testcase Planning Development
UVM Testbench Coding
IP SOC Verification
Design Verification Failure Debugging
Concepts in Digital Design
About Company
Skills:
Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV
Skills:
Design Verification, Debugging RTL Verilog designs
Skills:
DDR, Ethernet, System Verilog, RISC-V cores, SV coverpoints, GIC, CMN, AXI protocol, SMMU, Low-power verification, PCle, Cache and coherency verification, Uvm, UPF, ACE protocol, eMMC, CoreSight, Low-speed peripherals, ARM v8 and v7 cores, Assembly
Skills:
Perl, Python, Tcl, Functional Coverage, Uvm, SVA, systemverilog, ASIC SoC Subsystem IP verification
Skills:
Pcie, Regression Testing, Verilog, Ethernet, assertions, Uvm, systemverilog, functional coverage, constrained-random verification