Design Verification Engineer

Responsibilities:

• Perform pre-Si verification on various IP blocks and full-chip of FPGA/ASIC designs.
• The job scope includes test plan definition, System Verilog/UVM test bench and content development, debugging and running regression to deliver good-quality design.
• Candidate will work closely with team and interact with product/IP architect, logic design engineer, DFX owner, and design automation engineer to ensure high quality design validation.

This role is to be based in Penang, onsite. Experienced candidates will be considered for KL location, onsite.

Qualifications:

• BSEE/MSEE/PhD with 3 years experience or more. Fresh graduate applications with CGPA 3.5+ will be considered.
• Mandarin-speaking is a MUST-HAVE requirement.
• Experience in functional verification that may include test planning, test bench development, stimulus generation, reference model and assertion checkers development and functional coverage.
• Experience with modern verification techniques e.g. System Verilog OVM/UVM, assertion-based verification, constrained random verification methodologies.
• Familiar with IP protocols (e.g. HSST, Ethernet, PCIe, DDR), FPGA and/or ARM architectures.
• Hands-on experience in various logic designs and verification tools and flow e.g. from Cadence, Mentor Graphics and/or Synopsys.