Design Verification Engineer

Responsibilities

• Apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC design.
• Work independently on various DV tasks and providing technical guidance to the DV team.
• Involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.
• Perform USB-IF compliance testing

Requirements

• Pre-silicon UVM experience
• Good understanding on ASIC/SOC design flow.
• Strong coding with Verilog and SystemVerilog
• Good knowledge of design verification methodology UVM.
• Strong experiences with sequence creation, functional cover groups and assertion coding.
• Strong C/C++ software development experiences
• Familiar with scripting language such as Perl, C shell, Makefile, Ruby
• Familiarity with industry-standard high-speed protocols – USB Technical Skills/Expertise:

a. Synopsys VC Verification IP (VIP) for USB;

b. USB traffic generators and checkers;

c. Oscilloscopes for signal validation

• Bachelor Degree or M.S. in Electrical Engineering or Microelectronics.