Verify designs for DRAM (e.g., LPDDR4/5, DDR4/5, HBM) protocol compliance and functionality through rigorous testing and simulation.
Develop and execute design verification plans to ensure functional correctness and compliance with specifications.
Perform power-aware simulations and ensure low-power design compliance using UPF (Unified Power Format) standards.
Develop and maintain reusable verification environments, including testbenches and test cases, using industry-standard methodologies (e.g., UVM).
Debug functional errors in the RTL model using simulation and debug tools with an in-depth understanding of the DRAM protocol and memory controller microarchitecture.
Define and implement functional coverage.
Perform coverage analysis and identify testing gaps.
Requirements:
Possess 5-10 years experiences in USB/DRAM design verification.
Strong coding with Verilog and SystemVerilog.
Good knowledge of design verification methodology UVM.
Experiences with sequence creation, functional cover groups and assertion coding.
Strong C/C++ software development experiences.
Familiar with scripting language, such as Perl, C shell, Makefile, Ruby.
