Design Verification Engineer

Ovm, System Verilog, FPGA verification, validation test suites, Design Verification, Uvm, constrained random verification methodologies, FPGA prototyping, FPGA architecture

Perl, System Verilog, Python, Tcl, Verilog RTL design verification, Modeling concepts, ASIC SoC design concepts, Uvm, Testbench development, DFT Scan BIST, JTAG protocols 1149.1 1500 1687

DDR, Usb, Pcie, Ethernet, Simulation and debug tools, Assertions SVA, Functional verification methodologies, Protocol verification, Uvm, systemverilog, Coverage-driven verification

DDR, Pcie, Ethernet, Debugging, System Verilog, test bench development, test plan definition, Cadence, Uvm, assertion-based verification, ARM architectures, HSST, Functional Verification, Regression, Mentor Graphics, constrained random verification, Synopsys

Perl, Vcs, Bash, Python, Axi, PCIe protocol, PIPE, Cadence, Synopsys, Uvm, systemverilog