Responsibilities include (but are not limited to):
- Develop and implement comprehensive DFT architectures to ensure high testability of integrated circuits (ICs).
- Design and verify DFT logic and components, focusing on MBIST, Scan Chains, and Boundary Scan (JTAG) implementations.
- Generate and optimize test patterns, including ATPG, compression logic, and power-aware scan chains, using tools like Synopsys TetraMax and Tessent FastScan.
- Perform scan stitching and ensure controllability and observability within designs for effective fault detection.
- Conduct Gate Level Simulations (GLS) and other verification methodologies to analyze DFT implementations.
- Analyze Design Rule Checks (DRCs), address manufacturing issues, and propose solutions to optimize fault coverage.
- Collaborate on silicon bring-up, diagnosis, and debugging during the product lifecycle.
- Automate DFT processes with scripting languages like Python, Perl, or Tcl for efficiency.
Requirements
- Minimum of a Bachelor's degree in Electronic/Electrical Engineering, Computer Engineering, or equivalent.
- Minimum 5 years of experience in DFT field.
- Proficiency in chip design languages: Verilog and SystemVerilog.
- Hands-on experience with ATPG tools (e.g., Synopsys TetraMax, Tessent TestKompress).
- Expertise in simulation tools such as Synopsys VCS or Cadence Xcelium for test pattern validation.
- Familiarity with debugging tools like Synopsys Verdi or Cadence SimVision.
- Knowledge of EDA tools such as Synopsys DFT Compiler, Tessent MBIST, and compression techniques.
- Scripting proficiency in Python, Perl, or Tcl to enhance workflow automation.
- Strong analytical skills for fault coverage analysis, test pattern optimization, and resolving DRC violations.
