Electrical Engineer

Job Description:

• Path Delay Fault content and test-pattern generation, analysis, and debug, DFT/ATPG concepts, including scan and transition-delay fault coverage
• Test-pattern generation, simulation, and failure analysis
• Digital logic and semiconductor product development
• Static timing analysis and timing-closure concepts
• Familiarity with Verilog/SystemVerilog and scripting using Tcl, Python, or Perl
• Lab, silicon, or product-level debug experience
• Ability to analyze test data and communicate root-cause findings clearly

Key responsibilities

• Generate path-delay-fault test content, including test patterns, pattern documentation, and related test-flow materials
• Review and analyze ATPG output, simulation results, tester data, and failure signatures to improve generated content
• Investigate path-delay and timing-related failures and help determine root cause
• Correlate simulation, static timing, and silicon or product test results
• Support test coverage improvement, pattern quality, and debug efficiency
• Collaborate with DFT, design, validation, product engineering, and manufacturing teams
• Document analysis, debug results, root cause, and corrective actions
• Track issues to closure and provide clear technical status updates
• Follow established engineering processes, quality requirements, and project schedules