FEINT Engineer

We are seeking a highly motivated AI Silicon Design Engineer to accelerate front-end (FEINT) implementation flow with AI. This role combines a working knowledge of RTL-to-netlist implementation with AI/ML technologies, and focuses on building and applying AI agents, skills and workflows that improve the productivity and turnaround of synthesis, constraint, CDC/LINT, low-power and timing analysis tasks. The ideal candidate has a solid foundation in front-end implementation or EDA flow automation, along with hands-on experience developing AI solutions for engineering workflows.

Key Responsibilities:

• Develop AI agents and skills that automate front-end implementation tasks: run launch and monitoring, QoR and area/timing regression reporting, constraint and waiver review, and timing debug
• Apply LLMs and agentic AI to automate tasks such as synthesis timing violation root-cause analysis, CDC/LINT waiver triage, UPF comparison, netlist quality review, and regression failure analysis
• Build AI-powered engineering workflows using Python, MCP, agent frameworks, vector databases and modern GenAI platforms
• Support front-end flow execution: launch power-aware synthesis runs, generate and check constraints, run CDC/RDC/LINT and netlist quality checks, and prepare the results for engineering review
• Package and document AI skills and agents so that other engineers can reuse them, and publish them to the team's shared repository
• Work with front-end engineers to identify repetitive tasks worth automating, and validate that automated results match manual review
• Report progress, results, and the measured time savings of the workflows delivered

Requirement:

• Bachelor or above degree in Electrical Engineering, Microelectronics, Integrated Circuit Science, Computer Engineering, Computer Science, or a related field
• 3+ years of experience in front-end implementation (synthesis, static timing analysis, CDC/RDC/LINT, or low power) or in EDA flow and tool development
• 1+ year of practical experience applying AI/ML or Generative AI technologies
• Working knowledge of Verilog/SystemVerilog and the RTL-to-netlist flow
• Experience with front-end EDA tools and flows (Fusion Compiler, PrimeTime, Formality/Conformal LEC, VSI/VCLP, SpyGlass/0-In for CDC/RDC/LINT)
• Experience with Generative AI / LLMs, prompt engineering, and AI agent workflows
• Strong Python and Tcl programming skills, with experience in Git, Linux, and scripting automation
• Familiarity with RAG architectures, MCP tools, and agent frameworks such as Claude Code skills/agents, LangChain, LangGraph, AutoGen, or CrewAI
• Familiarity with cloud AI platforms and AI-assisted software development tools
• Experience with physical design flows is a plus

Prefer to have

• Strong cross organizational communication skills
• Highly collaborative
• Ability to work well as a multi-site team
• Ability to multitask
• Problem solving and analytical ability
• Experience with large digital ASIC/SoC projects
• Experience building AI tools for EDA flow automation, debug acceleration, report generation, or design-quality checking
• Understanding of ML fundamentals, fine-tuning, embeddings, and vector databases
• Good English skills on talking, presentation and writing documents
• Experience working in a challenging engineering environment