We are seeking a Front End Integration Engineer to perform IP level FEInt tasks. The ideal candidate will have expertise in synthesis, linting, CDC (clock domain crossing), LEC (logical equivalence checking), UPF (Unified Power Format), and other relevant areas.
Responsibilities:
- Conduct synthesis and optimization of IP blocks Perform linting to ensure code quality and adherence to design guidelines.
- Conduct CDC analysis to identify and address potential issues in clock domains.
- Perform LEC to ensure design consistency before and after synthesis.
- Implement UPF for power management in the design
Qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
- At least 5 years of experiences in synthesis, linting, CDC, LEC, and UPF Prior experience in front end integration tasks.
- Proficient in industry standard EDA tools.
- Strong problem-solving and analytical skills.
- Good communication and teamwork skills.
- Rich verification experience (Block or SoC level, simulation, formal verification(plus)).
- Strong UVM, System Verilog, C++ , Perl, Python knowledge.
- Strong Debug capabilities, master VCS/Verdi/DVE tools.
- Familiar with Standard AMBA/AXI/AHB interface protocol.
- Good problem-solving and communication ability.
