Lead Design Verification Engineer
Lead Design Verification Engineer
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Job Description
Lead Design Verification Engineer
Location: Bengaluru
Experience: 6–12 Years
Role Overview
We are looking for a strong Lead Design Verification Engineer with deep expertise in Ethernet protocol & compliance verification, SerDes/controller validation, and UVM environment development to drive verification of complex networking and high-speed interface IPs.
Key Responsibilities
- Own verification strategy, planning, execution, and signoff for Ethernet/SerDes/controller IPs.
- Develop scalable, reusable SystemVerilog/UVM verification environments.
- Drive Ethernet protocol and compliance verification across functional, corner-case, and error scenarios.
- Perform SerDes and Ethernet controller validation, including link training, data integrity, error handling, and interoperability.
- Develop UVM agents, sequences, scoreboards, monitors, assertions, coverage models, and protocol checkers.
- Drive constrained-random, coverage-driven, assertion-based, and regression verification.
- Debug complex RTL/protocol issues using simulation, waveform, and regression analysis.
- Collaborate with RTL, architecture, firmware, PHY, and system teams to achieve verification closure.
Required Skills
- 6–12 years of hands-on Design Verification experience.
- Strong SystemVerilog, UVM, SVA, and verification methodology expertise.
- Hands-on experience in Ethernet protocol & compliance verification.
- Strong experience in SerDes/controller validation and high-speed interface verification.
- Proven expertise in UVM environment development and reusable verification infrastructure.
- Strong understanding of Ethernet MAC/PCS/PHY, link protocols, packet processing, and error handling.
- Experience with functional/coverage closure and complex protocol debug.
- Strong scripting skills in Python/Perl/Tcl are preferred.
Good to Have
- Experience with 10G/25G/50G/100G/200G/400G Ethernet.
- Exposure to Ethernet VIP, compliance testing, SerDes PHY, PCIe/CXL, or high-speed interconnects.
- Experience leading verification teams/projects and driving end-to-end verification signoff.
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
reusable verification infrastructure
PHY link protocols
UVM environment development
high-speed interface verification
Ethernet MAC
functional coverage closure
Ethernet protocol compliance verification
packet processing
complex protocol debug
SerDes controller validation
error handling
About Company
Skills:
Shell, Perl, Python, Tcl, Cadence Xcelium, Mentor QuestaSim, PCI Express, Uvm, systemverilog, Synopsys VCS, Assertion-Based Verification, Constrained Random Verification, Functional Verification
Skills:
Python, System Verilog, Systemc, Pcie, Hybrid test benches, MDV, DV signoffs, SV, CDV, Uvm, Simulation Scripts, test vectors, Coverage, Regression, UCIe, Axi, testplan creation, DV Infrastructure, building testbenches, stimulus based verification, SystemC based reference model
Skills:
Test Case Creation, Shell, Perl, Python, Advanced Debugging skills, Uvm, testbench development, coverage-driven verification, Computer Architecture concepts, Formal Verification techniques, Functional Verification, Rtl Design