Physical Design Engineer
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Physical Design Engineer
Job Summary
We are looking for a Physical Design Engineer with hands-on experience in ASIC physical design from Netlist to GDSII. The ideal candidate should have experience in physical implementation, timing closure, and physical verification for advanced technology nodes.
Job Type: Full Time - Onsite (Permanent and Contract)
Job Location: Penang, Malaysia
Job Mode: Onsite
Salary: Depends on your Skills and Experience
Position Open For: Person Legally authorized to work in Malaysia (No Visa Sponsorship)
Key Responsibilities
Requirements
Job ID: 151705631
Skills:
power integrity , Python, Routing, Perl, Tcl, IR drop, primetime, Design closure for setup hold timing, Cadence Innovus, LVS, SerDes PHY, DDR PHY, Timing Closure, StarRC, Placement, Timing signal integrity, Power Planning, floorplanning, DRC, Reliability requirements, Physical verification and signoff, Congestion analysis, PPA optimization, Synopsys ICC2
Skills:
EDA tools for physical design and verification, Floor Planning, digital design principles, CMOS processes, Timing Closure, multi-power domain analysis, low-power design techniques, clock design, Clock Tree Synthesis, RTL to GDS flows
Skills:
Shell, PYTHON, Static Timing Analysis, Tcl, Flex-H, power analysis, STA constraints, FinFET Dual Patterning nodes, Innovus, Physical Design, PD metrics dashboard scripts for QOR tracking, PNR flow from RTL to GDS flow, Multi-point CTS, Custom-CTS
Skills:
routing, power distribution planning, LEC, MBR flows, Floor Planning, design tools and flows, Low Power physical design flows, Power-Gating, clock network planning, Timing Closure, Clock-Gating, placement and optimization
Skills:
rc extraction , Timing ECO Implementation, Physical Design, Timing ECOs, Placement, floorplanning, Timing Closure, Routing and Optimization, Full-chip and Block-level Physical Implementation
