Great career growth opportunity in a leading RISC-V technology
Attractive compensation & benefits package with stocks
Job Description
Expert in place and route, static timing analysis and synthesis.
Responsibilities include all phases of physical implementation from floorplanning, powerplanning, place & route, CTS, formal verification and analysis including general timing, power, DRC and other quality of results.
Handle high speed and low-power design including clock gating, power gating and multi-voltage designs.
Develop physical constraints and optimization techniques for design convergence.
Perform analysis and provide engineering judgment for design challenges and necessary trade-offs.
You will have an opportunity to contribute to all aspects of physical design from synthesis through signoff including flow and methodologies.
Job requirements:
Bachelor / Master Degree in Electrical & Electronic or equivalent.
Experienced on advance process node SoC, IP, fullchip & partition, physical design implementation, timing closure & verification using Synopsys and/or Cadence solutions.
Experienced in physical verification (DRC & LVS) will be an added advantage.
Experienced in SoC design flow & methodology. Good knowledge in shell scripting, PERL and TCL.
