Physical Design Lead / Validation Engineer

Physical Design Lead/ Engineer

Responsibilities:

1.Responsible for digital circuit back-end design, completing the full digital APR (Automatic Place and Route) flow from netlist to GDS, including floorplanning, clock tree synthesis (CTS), placement, routing, and final GDS generation; experience with top-level design is preferred.

2.Perform physical verification such as DRC and LVS on the GDS output to ensure design integrity.

3.Communicate effectively with design engineers to fully understand design requirements and resolve technical challenges during the design process.

4.Participate in developing IC-related technical documentation and preparing design reports.

Requirements:

1.Bachelor's degree or above, with at least 2 years(Lead with 5yrs+) of experience in digital APR; experience in top-level or subsystem design is preferred.

2.Major in Microelectronics, Computer Science, or Electronic Engineering.

3.Proficient with back-end design tools such as Innovus, Calibre, StarRC/QRC, PrimeTime (PT), Redhawk, and Virtuoso.

4.Solid understanding of integrated circuit process and design fundamentals; with strong logical and analytical skills; experience in advanced process node technologies is a plus.

5.Responsible, proactive, and detail-oriented, with strong teamwork and communication skills.

Validation Engineer

Responsibilities:

1.Post-silicon bring-up and validation of internal IPs on complex SoC platforms.

2.Collaborate with architecture, design, and firmware teams to understand IP specifications and

develop validation strategies.

3.Develop and execute test plans for functional validation of peripheral IPs (e.g., PCIe, USB,

eSPI, I2C, I3C).

4.Debug and resolve silicon and system-level issues through hands-on lab work and analysis.

5.Document validation results, findings, and recommendations for design and system

improvements.

Requirements:

1.Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.

2.Strong understanding of computer architecture and high-speed peripheral protocols.

3.Hands-on experience with post-silicon validation, lab equipment, and debug tools.

4.Familiarity with SoC system integration and low-level firmware interaction is a plus.

5.Excellent problem-solving skills and ability to work in a collaborative environment.