Physical Design | STA

Responsibilities:

• Drive full-chip and block-level physical implementation, including floor planning, placement, clock tree synthesis (CTS), routing, and optimization.
• Perform timing closure across multi-corner, multi-mode (MCMM) conditions, ensuring compliance with performance, power, and area (PPA) goals.
• Conduct static timing analysis (STA) using PrimeTime or equivalent tools, including timing ECO implementation and signoff validation.
• Perform physical verification (DRC/LVS), crosstalk analysis, and EM/IR checks to ensure design reliability and manufacturability.
• Collaborate with front-end design, STA, and power teams to resolve timing, congestion, and design rule issues efficiently.
• Develop and maintain methodology scripts (Tcl, Perl, or Python) to automate and streamline physical design and STA workflows.
• Utilize advanced PnR tools such as Synopsys ICC2/ICC, Fusion Compiler, or Cadence Innovus for implementation and optimization.
• Support tape-out activities, including design signoff and physical database management.

Requirements:

• Bachelor's or Master's degree in Electrical/Electronic Engineering or a related field.
• At least 2-8 years of experience in ASIC physical design (PnR and STA focus).
• Strong hands-on experience with FinFET and advanced nodes (16nm, 14nm, 12nm, sub-10nm).
• Proficiency in timing analysis, optimization, and closure using Synopsys PrimeTime or equivalent.
• Experience in PNR implementation flows using Synopsys ICC2/Fusion Compiler, or Cadence Innovus.
• Solid understanding of design constraints (SDC), RC extraction, and timing ECOs.
• Knowledge of physical verification tools (Calibre, StarRC, Redhawk) is a plus.
• Proficient in scripting languages such as Tcl, Perl, and Python.
• Excellent analytical and problem-solving skills, with attention to detail and ability to work in a fast-paced environment.
• Willing to work in Bayan Lepas, Penang Malaysia.