Principal Engineer - Physical Design

PRINCIPAL ENGINEER – PHYSICAL DESIGN

Location: Bayan Lepas, Pulau Pinang

Working Arrangement: Hybrid (3 days WFO + 2 days WFH)

We are seeking an experienced Principal Engineer – Physical Design to lead ASIC physical design activities from floorplanning to GDSII convergence. This role is responsible for driving physical implementation strategies, timing closure, low-power design methodologies, and design verification while ensuring high-quality tapeouts. The successful candidate will also play a key role in developing best-in-class design flows, methodologies, and mentoring junior engineers within the team.

Key Responsibilities:

• Understand design data flow and complexity, translating requirements into physical design constraints and strategies to achieve optimal PPA (Power, Performance, Area).
• Define and optimize floorplanning strategies, place-and-route implementation, and timing closure within specified power targets.
• Implement low-power physical design methodologies, including Power Gating, Clock Gating, and Multi-Bit Register (MBR) flows.
• Perform and debug Logic Equivalence Checking (LEC) to ensure design equivalence against synthesized gate-level netlists.
• Drive physical design convergence from floorplanning through GDSII signoff.
• Lead and mentor junior engineers through effective coaching and technical guidance.
• Enhance design tools, flows, and methodologies to improve turnaround time (TAT) and design efficiency.
• Collaborate with global project teams to resolve technical issues and ensure project milestones, quality, and schedules are met.
• Support design verification, audit, and signoff activities to ensure successful tapeout.

Requirements:

• Bachelor's or Master's Degree in Electrical Engineering or equivalent.
• 6–10 years of ASIC/IC development experience in a fast-paced semiconductor environment.
• Proven experience in completing complex ASIC/IC tapeouts on VDSM process technologies.
• Experience driving large design blocks to timing closure, physical design closure, and DRC/LVS signoff.
• Strong understanding of physical design methodologies, VDSM effects, and related debugging techniques.
• Knowledge of floorplanning, placement, timing optimization, clock tree synthesis, power planning, and routing.
• Hands-on experience with Synopsys ICC/PT, Cadence Innovus, and ETS.
• Experience with post-layout physical verification and DFM rule checks using Cadence PVS or equivalent tools.
• Strong understanding of Low Power methodologies, Static Timing Analysis (STA), Signal Integrity, and Power Integrity.
• Experience in scripting using TCL, Perl, and Shell.
• Working knowledge of Verilog, VHDL, UNIX, and Linux environments.
• Excellent analytical, problem-solving, verbal, and written communication skills.
• Ability to lead, mentor, and collaborate effectively in a challenging and dynamic environment.

Added Advantages:

• Knowledge of synthesis tools such as Synopsys Design Compiler, Cadence Genus, or equivalent.
• Experience with static timing analysis tools such as Synopsys PrimeTime or equivalent.