Principal Engineer Physical Design

Principal Engineer – Physical Design

Location: Bengaluru, India

Experience: 12–18 Years

Role Overview:

We are looking for a Principal Engineer – Physical Design with 12–18 years of experience in full-chip physical implementation, timing closure, power integrity, and signoff of advanced SoC designs. The ideal candidate will possess deep expertise in Cadence Innovus, EMIR analysis, Static Timing Analysis (STA), ECO implementation, and physical design signoff.

Key Responsibilities

• Lead full-chip physical design implementation, including floorplanning, placement, CTS, routing, optimization, and physical signoff.
• Drive timing closure across PVT corners, including setup, hold, MCMM analysis, and critical path optimization.
• Own physical implementation and optimization using Cadence Innovus, ensuring design quality, performance, and schedule adherence.
• Perform and drive Static Timing Analysis (STA), identifying timing bottlenecks and implementing corrective measures.
• Lead EMIR (Electromigration and IR Drop) analysis, power integrity checks, and resolution of power-related violations.
• Drive ECO implementation for timing, congestion, power, and functional requirements while maintaining design integrity.
• Manage physical design signoff activities, including timing, physical verification, DRC/LVS, IR drop, electromigration, and other relevant checks.
• Collaborate with front-end design, synthesis, STA, DFT, and verification teams to resolve cross-functional design issues.
• Analyze and resolve congestion, routing, signal integrity, antenna, and other physical implementation challenges.
• Develop and optimize physical design methodologies, flows, and automation to improve PPA and execution efficiency.
• Provide technical mentorship and drive design closure for complex SoC projects.

Required Technical Expertise

• 12–18 years of hands-on experience in VLSI Physical Design, with strong full-chip implementation experience.
• Expertise in Cadence Innovus for place-and-route, optimization, and physical implementation.
• Strong understanding of full-chip physical design flow from netlist to signoff / GDSII.
• Deep expertise in Static Timing Analysis (STA), timing constraints, setup/hold closure, and MCMM analysis.
• Strong experience in EMIR analysis, power integrity, IR drop, and electromigration closure.
• Hands-on experience with ECO implementation, including timing ECOs, functional ECOs, and physical optimization.
• Experience in physical design signoff and closure of complex SoC designs.
• Strong understanding of floorplanning, placement, CTS, routing, congestion management, and PPA optimization.
• Proficiency in Tcl/Perl/Python scripting for flow automation and physical design analysis.
• Experience working with advanced technology nodes and complex SoC architectures is preferred.

Preferred Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related discipline.
• Experience delivering complex, high-performance SoCs through physical design signoff.
• Strong debugging, analytical, and problem-solving capabilities.
• Demonstrated technical leadership in physical design implementation and signoff closure.
• Ability to collaborate effectively across cross-functional engineering teams.

What You Will Drive

• Full-chip physical implementation and signoff ownership.
• Timing, power, and area optimization across advanced SoC designs.
• Physical design closure, ECO execution, and signoff readiness.
• Technical excellence and methodology improvements within the physical design organization.