RTL Design Engineer
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Position: RTL Design Engineer
Experience: 5 - 8 Years
Qualifications: BE/Btech in ECE/EEE
Responsibilities -
Job ID: 153636533
Skills:
conformal lec , Perl, Verilog, Python, Tcl, VC spyglass, IPXACT, IORING, LINT, Formality, VSI, UPF, Design Partitioning, Phys GPIOs, SoC IP level Integration, RTL Coding
Skills:
Perl, Verilog, Python, Makefiles, RTL Build flows, Chip Design Functions, SoC Verification, Physical Design, Rtl Design, Dft, Synthesis, System-On-Chip design implementation flow
Skills:
Tcp Ip, Pcie, Perl, Shell scripting, Ethernet, RDMA IPs, VCS simulation tool, Silicon IP development process methodologies, Verilog RTL design, Design for Test methodologies, DMAs, NVMe based Storage IP
Skills:
Verilog, Ethernet Protocols, LINT, Rtl Design, spyglass, Synthesis, cdc, RDC, PPA optimization, systemverilog
Skills:
Automation Frameworks, Sta, LINT, Memory operation, Synchronous design concepts, power analysis, SoC design flows, CMOS Circuit Design, Rtl Design, spyglass, Synthesis, device physics, CDC methodologies
