Senior Design Verification Engineer
Senior Design Verification Engineer
ALTEN Calsoft LabsEarly Applicant
- Posted 2 months ago
- Be among the first 10 applicants
Job Description
Senior Design Verification Engineer
Location: Bangalore.
Experience: 4 to 10 Years.
Notice Period: Any.
- Perform verification of complex digital designs at block and system level.
- Develop testbenches using SystemVerilog/UVM for simulation and debugging.
- Create and execute comprehensive test plans for functional verification.
- Achieve coverage targets using code and functional coverage metrics.
- Work closely with RTL design and architecture teams to identify issues.
- Debug simulation failures and trace root causes effectively.
- Run regressions and maintain automated verification flows.
- Familiarity with formal verification and assertion-based techniques.
- Proficient in tools like VCS, Questa, Verdi, and waveform viewers.
- Experience with scripting languages like Python, Perl, or Tcl.
- Strong analytical, problem-solving, and communication skills.
- Bachelor's or Master's degree in Electronics, Electrical, or related field.
About Company:
ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.
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About Company
Skills:
Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV
Skills:
Usb, DDR, Perl, Pcie, Ethernet, Python, Tcl, Uvm, coverage-driven verification, systemverilog, digital design RTL understanding, AMBA, MIPI, SVA
Skills:
SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification
Skills:
Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog
Skills:
Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog