Senior Design Verification Engineer

Job Summary:

We are seeking a highly skilled Design Verification Engineer (DV) with 7-10 years of experience to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits

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Responsibilitie

• s:Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verificatio
• n)Design and create high-quality verification environments (testbenches) to achieve exceptional code covera
• geUtilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionali
• tyDebug and analyze verification failures with a keen eye to identify and resolve the root cause of design issu
• esCollaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adheren
• ceLead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environme
• ntParticipate in code reviews and champion best practices for verification code quali
• tyStay current with the latest advancements in verification tools and methodologi

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Qualificatio

• ns:Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a pl
• us)7-10 years of solid experience in Design Verification for ASICs or S
• oCsIn-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machin
• es)Proven ability to develop, debug, and optimize complex verification environme
• ntsExpertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Form
• al)Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Pe
• rl)Experience in PCIe, UCIe, DDR,Ethernet is a p

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Benef

• its:Competitive salary and benefits package commensurate with experi
• enceOpportunity to work on leading-edge technologies and projects with a high im
• pactCollaborative and dynamic work environment that fosters continuous lear
• ningPotential for professional development and career advance