Senior Design Verification Engineer
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Experience:4+ years
Notice Period:0 to 30days
Location:Bangalore
Job Description.
1.Must Have: SoC or IP
2.Experience Languages : System Verilog (must)
3.Methodologies: OVM/UVM/VMM
4.Protocols:DDR/USB/Ethernet/PCIE/Video/HDMI/MIPI/DSI/CSI
5.Processor/ARM Based SoC Verification experience
6.Strong Analytical skills desirable if having worked.
Job ID: 151583041
Skills:
Jasper, Perl, Python, Asic verification, verification methodologies, Synopsys Magellan, Uvm, systemverilog, Cadence IEV, VC Formal, functional coverage, SVA
Skills:
Verilog, Python, Synopsys VCS, Cadence Incisive, formal verification, VHDL, Modelsim, Uvm
Skills:
Computer Architecture, Vcs, DDR, Pcie, Perl, Ethernet, Python, Verdi, ARM-based SoC architecture, CHI, Xcelium, SystemVerilog UVM, Axi, APB, HBM, Questa, AHB, SVA
Skills:
testability , systemverilog, SoC IP verification methodologies, Uvm, DFX DFT concepts, ATPG, multi-level verification
Skills:
bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, full verification life cycle, vector processing units, industry-standard simulators, AI ML Accelerators, systemverilog, hierarchical memory subsystems, revision control systems, Specman E, constrained-random verification environments, Verification, IP subsystem SoCs, packet processing, congestion control, regression systems, Debug
