Senior Design Verification Engineer, Silicon
Senior Design Verification Engineer, Silicon
Google India8-10 Years
- Posted 17 hours ago
- Be among the first 10 applicants
Job Description
Minimum qualifications:
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Bachelor's degree in Electrical Engineering, Computer Engineering or equivalent practical experience.
- 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
- Experience in developing and maintaining verification test benches, test cases, and test environments.
- Master's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- Experience with low power, debug, Gate-Level Simulation (GLS) and formal verification.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Plan the verification of complex digital design blocks at sub system level by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
More Info
Job Type:
Industry:
Employment Type:
Key Skills
Low power debug
SystemVerilog Assertions (SVA)
Constrained-random verification environments
Verification test benches
Formal tools
Verification methodologies
Gate-Level Simulation (GLS)
Coverage measures





