Job Details
Job Description:
DFT Architecture & Implementation
- Define, implement, and maintain DFT strategies for FPGA designs to meet quality, coverage, and manufacturability goals.
- Hands-on implementation and debug of DFT features including Scan Architecture, Scan Insertion, ATPG pattern generation and coverage analysis, Cell-Aware, Power Aware, Memory BIST and Repair, Streaming Scan Network (SSN), ICL extraction & PDL retargeting
- Strong knowledge on industrial test standards IEEE 1149.1 (JTAG) and/or IEEE 1687 (IJTAG)
- Drive DFT sign-off using industry tools including review RTL, Netlist & Test Plan for DFT compliance & testability risks
- Support post-silicon power-on, test content debug & coverage optimization
Timing & Physical Design Collaboration
- Develop and validate timing constraints for DFT logic
- Work closely with Front End IP Design & Physical Design teams to meet timing closure for DFT paths
- Resolve congestion, clocking, and scan-related issues
- Support custom DFT logic integration where needed
Methodology & Cross-Functional Collaboration
- Develop, improve, and document DFT methodologies and best practices
- Mentor junior engineers and review DFT implementations
- Participate in architecture reviews and design trade-off discussions
Qualifications
Required Qualifications
- Bachelor's or Master's degree in Electrical / Electronic Engineering or related field
- 7+ years of industry experience in DFT design, preferably in FPGA or ASIC-like FPGA flows
- Solid understanding of DFT methodologies and fault models
- Experience working with custom design blocks & PNR flows
- Strong collaboration experience with physical design and timing teams
- Proficiency in Verilog or SystemVerilog
- Hands-on experience in DFT design verification is a plus
- Good debugging, problem-solving, and communication skills
- Exposure to AI or LLM implementations in FPGA or SOC design is a plus
Additional Experiences
- Knowledge or experience in Functional Safety standards
- Experience with post-silicon debug, yield learning, and test optimization
- Exposure to ATE platforms and production test flows
- Knowledge of low-power DFT, clock gating, and test power reduction techniques
- Experience with DFT for complex SoC-like FPGA architectures, high-speed interfaces or mixed-signal blocks
- Experience in development of DFT automation or flow development
- Scripting skills (Python, Tcl, Perl) for automation and analysis
- Experience with DFT or Debug Design Verification
- Experience working in cross-site or global teams
Job Type
Regular
Shift
Shift 1 (Malaysia)
Primary Location:
Penang 15, Penang, Malaysia
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
