Job Description :
- Participate in DFT architecture definition;
- Perform DFT features implementation and verification.
- Develop/improve Scan and MBIST insertion flow;
- Perform ATPG simulation, pattern generation and fault coverage analysis;
- Perform MBIST insertion, validation and pattern generation;
- Create and maintain DFT timing constraints;
- Work with Test Engineers to bring-up test patterns on ATE and debug test pattern failures;
- Work with Designers to drive testability issues to closure.
This role can be located in Penang or KL
Requirements :
- Minimum of 3 years of working experience in DFT implementation and validation for complex SoC designs;
- Knowledge of DFT (JTAG/SCAN/MBIST) concepts, architecture and methodology;
- Strong knowledge and experience in Scan Insertion , TestKompress and generating ATPG vectors for Stuck-At and At-Speed Faults.
- In-depth experience in analyzing and improving scan coverage;
- Hands on experience in MBIST, experience in Boundary Scan, inserting tap controller and P1500;
- Strong debug and validation skills;
- Strong communications and stakeholder management skills
- Self-motivated, with proven collaboration and leadership skills
