Job Summary
We are looking for a skilled DFT Engineer to drive Design for Testability (DFT) implementation for complex SoC/ASIC designs. The role involves designing and integrating test structures, generating test patterns, and supporting silicon bring-up to ensure high test coverage and product quality.
Key Responsibilities
- Design and implement DFT architectures, including Scan insertion, MBIST (Memory BIST) and LBIST (Logic BIST)
- Perform ATPG (Automatic Test Pattern Generation) and analyze test coverage
- Implement and optimize test compression techniques to improve efficiency
- Debug test failures during pre-silicon and post-silicon stages
- Support silicon bring-up and validation activities
Work closely with:
- Verification teams for DFT validation
- Physical Design (backend) teams for DFT implementation and closure
- Ensure compliance with DFT methodologies and quality standards
- Analyze and resolve coverage gaps and testability issues
- Support production test readiness and yield improvement
Education:
Bachelor´s or Master´s degree in in
Electronics / Electrical / VLSI Engineering.
Experience:
- Experience in DFT / VLSI design.
- Hands-on experience in SoC/ASIC DFT implementation.
- Exposure to full-chip or block-level DFT flows.
- Experience with advanced nodes is a plus.
- Exposure to silicon bring-up and post- silicon validation
Technical Skills:
Strong experience with:
- Synopsys DFT Compiler
- Mentor/Tessent (Siemens Tessent)
Expertise in:
- Scan architecture and insertion
- ATPG and fault modeling
- Test compression techniques
- Boundary scan (JTAG) implementation
Good understanding of:
- Digital design fundamentals
- Timing and physical design constraints related to DFT
- Familiarity with scripting (Tcl/Python) is an added advantage
