Senior Engineer, APTD CEM - Advanced Packaging Die Level Technology Engineering

About WhiteCrow

We are global talent research, insight, and sourcing specialists with offices in the UK, USA, Singapore, Malaysia, Hong Kong, Dubai, and India. Our international reach has helped us to understand and penetrate specialist markets at a global level. In addition to this, our service is also extended to complement our client's in-house talent acquisition teams.

About our client

Our client is a global technology leader specializing in advanced memory and storage solutions that power next-generation computing and data-driven applications. With strong expertise in semiconductor innovation, the organization develops high-performance memory technologies across DRAM, NAND, and storage platforms for applications spanning data centers, artificial intelligence, mobile devices, client computing, and intelligent edge ecosystems.

Driven by a commitment to technology advancement, operational excellence, and customer-centric innovation, the company plays a significant role in enabling modern digital infrastructure and compute-intensive workloads worldwide.

As a Senior Engineer, APTD CEM - Advanced Packaging Die Level Technology Engineering, you will be responsible for...

• Developing and optimizing assembly processes for advanced packaging technologies, including wafer-level packaging, Chip-on-Wafer (CoW), and Chip-to-Wafer (C2W) die stacking.
• Improving product quality, yield, productivity, and manufacturing cost.
• Driving process management projects supporting future technology nodes.
• Evaluating, qualifying, and implementing new equipment and materials.
• Establishing process parameters for semiconductor manufacturing equipment.
• Ensuring robust quality through process monitoring, inspection, testing, SPC, DOE, and defect analysis.
• Using data analytics to establish advanced process controls and identify improvement opportunities.
• Collaborating with Package Integration, Assembly Engineering, Front-End Wafer Fab, Assembly/Test Engineering, Product Engineering, and Global Quality teams.
• Supporting seamless transition from product development through qualification into High Volume Manufacturing (HVM).
• Providing Process of Record (POR) and Model of Record (MOR) documentation.

What you already have...

• B.S./M.S./Ph.D. (or equivalent) in Materials Science, Chemical Engineering, Electrical Engineering, Mechanical Engineering, Physics, or related technical discipline.
• 2+ years of semiconductor process development or equipment evaluation experience, preferably in wafer bonding, die stacking, or advanced packaging.
• Proficiency in Python, R, and SQL.
• Experience with Visual Basic for automation and tool integration.
• Knowledge of E3, FDC (Fault Detection and Classification), and RMS (Recipe Management System).
• Strong data analytics capability supporting SPC, DOE, defect analysis, and dashboards.
• Strong understanding of semiconductor process flows, yield, performance, and reliability.
• Strong problem-solving and root-cause analysis skills.
• Ability to work effectively under aggressive timelines and limited resources.

Skills: Advanced Semiconductor Packaging, Micro-Bump & Fine-Pitch Interconnects, Wafer Dicing & Die Singulation, Hybrid Bonding, Underfill & Encapsulation Technologies.