Senior Engineer - ASIC Verification

Location: Bayan Lepas, Pulau Pinang

We are seeking a Senior Engineer I - ASIC Verification to join our client's Semiconductor Manufacturing organization in Bayan Lepas, Penang. In this role, you will be responsible for verifying DDR4/DDR5 memory controller and AXI interface IPs, ensuring protocol compliance, functional correctness, data integrity, and optimal performance for high-speed memory subsystems.

Key Responsibilities:

• Develop and maintain SystemVerilog UVM-based verification environments for DDR4/DDR5 memory controller and PHY IP.
• Define verification plans, design testbenches, and create directed and constrained-random testcases.
• Write and debug testcases and sequences for DDR protocol features (read/write operations, refresh, training, power-down modes).
• Validate ECC, parity, and command/address/data integrity mechanisms.
• Develop and debug scoreboards, assertions (SVA), and checkers for data integrity and protocol correctness.
• Integrate AXI, APB VIPs with DDR subsystem.
• Perform coverage analysis (code, functional, assertion) to ensure verification completeness.
• Debug RTL and simulation failures using waveform analysis (SimVision, Verdi).
• Work with design teams to debug RTL and root-cause functional/timing issues in RTL and GLS.
• Collaborate with post-silicon and firmware teams on memory bring-up, validation, and issue resolution.
• Mentor junior verification engineers and promote verification best practices across the team.

Requirements:

• B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or Computer Engineering.
• Have 10 years of experience in SoC or IP-level verification, preferably in memory subsystem verification.
• Strong knowledge of DDR protocol (JEDEC specifications).
• Extensive hands-on experience with SystemVerilog, UVM, and industry-standard verification methodologies.
• Hands-on with simulation tools like Synopsys VCS, Cadence Xcelium, or Mentor Questa.
• Good understanding of memory controller architecture and timing parameters (setup/hold, tRCD, tRP, etc.).
• Knowledge of AXI protocol and its integration with DDR controller.
• Familiarity with assertions (SVA), scoreboarding, and functional coverage. Familiarity with GLS is a plus.
• Drive debug efficiency improvements by leveraging modern methodologies, script automation (Python), and integrating AI/LLM-assisted workflows to accelerate root-cause analysis and triage.