Senior Package Design Engineer

Job Responsibilities:

1. Evaluate and select chip packaging solutions, including assessment of substrate/package factory capabilities, BOM formulation, packaging size/stacking specification and ballmap layout.

2. Collaborate with internal and customer backend teams for bump selection, layout, and verification.

3. Iterative design of high-speed Serdes, DDR, HBM PHY. Packaging development related to IPs.

4. Design of packaging substrates and related document outputs, including substrate layout, POD, gerber, assembly instructions, etc.

5. Collaborate with SI/PI teams and system design teams for packaging optimization.

6. Coordinate and assist in problem-solving during production stages, conduct failure analysis, and assist in process improvements at packaging factories.

7. Develop advanced packaging 2.5D, 3D processes, and packaging technologies.

Job Requirements:

1. Bachelor's degree or above in semiconductor packaging / materials / mechanical engineering, with more than 8 years of full-time packaging design experience.

2. Familiarity with and understanding of process flows and design points of FCBGA, FCCSP, WLCSP, WLBGA, MCM, SiP and other packaging types. Proficiency in using Cadence APD and AutoCAD.

3. Understanding of various performance indicators and key points in packaging.

4. Familiar with packaging-related reliability testing standards.

5. Experience in 2.5D/3D packaging is a plus.

6. Strong team spirit, willing to communicate and share knowledge