Senior PCIe Electrical Validation Engineer (Gen5/Gen6)

About the Role

We are looking for an experienced Senior PCIe Electrical Validation Engineer to support next-generation high-speed interface validation, focusing on PCIe Gen5/Gen6 compliance, electrical characterization, and platform-level debugging.

This role offers the opportunity to work with advanced high-speed I/O technologies, perform hands-on lab validation, and troubleshoot complex PCIe link and signal integrity issues across next-generation platforms.

Key Responsibilities

• Perform PCIe Gen5/Gen6 electrical validation, compliance testing, and characterization in accordance with PCI-SIG specifications and CEM requirements.
• Set up and operate high-bandwidth oscilloscopes, BERT systems, and PCIe compliance fixtures for TX/RX testing and signal analysis.
• Bring up PCIe platforms and debug link training, device enumeration, link speed or lane degradation, and interoperability issues.
• Analyze TX/RX electrical performance, reference clock (Refclk), equalization, receiver margining, BER, jitter, and eye diagrams.
• Conduct signal integrity analysis and root-cause investigations for electrical compliance failures and high-speed interface issues.
• Collaborate with hardware, firmware, BIOS, silicon validation, and platform engineering teams to resolve complex system-level issues.
• Develop Python, Bash, Perl, or PowerShell scripts to automate validation, data collection, and test analysis.
• Support PCIe retimer and switch validation, interoperability testing, and post-silicon validation activities where applicable.

Requirements

• 6+ years of hands-on experience in PCIe or high-speed interface validation, electrical validation, or SerDes testing.
• Strong practical experience with PCIe Gen5 compliance and validation; exposure to PCIe Gen6 is highly desirable.
• Proven hands-on experience using high-bandwidth oscilloscopes and BERT systems for high-speed electrical measurements.
• Solid understanding of PCIe architecture, TX/RX, Refclk, LTSSM, link training, equalization, BER, jitter, eye diagrams, and signal integrity.
• Experience with PCIe platform bring-up, compliance debugging, and root-cause analysis of link or electrical failures.
• Familiarity with PCI-SIG specifications, CEM compliance, and high-speed test fixtures.
• Basic scripting skills in Python, Bash, Perl, or PowerShell for test automation and data analysis.
• Strong problem-solving skills and the ability to work effectively with cross-functional engineering teams.

Preferred Qualifications

• Hands-on PCIe Gen6 validation experience, including PAM4 signaling and FEC concepts.
• Experience with PCIe retimers, switches, and interoperability validation.
• Familiarity with post-silicon validation and platform-level debugging.
• Experience using Keysight, Tektronix, or Teledyne LeCroy test equipment.

If you have hands-on experience validating and debugging next-generation PCIe interfaces in the lab, we would love to hear from you. Please apply or reach out to discuss the opportunity.