Responsible for timing signoff at the chip level to ensure that the design meets timing requirements.
Collaborate with the front-end team to debug SDC files and complete the integration of module-level and full-chip-level SDC;
Collaborate with backend and DFT engineers to discuss and optimize the clock tree structure; Complete logical synthesis, check and optimize the pre-layout timing, and provide feedback on SDC-related issues.
Maintain, develop, and optimize STA processes to improve the efficiency and accuracy of timing analysis; 6. Responsible for Top STA timing analysis and quality control of SDC and various special inspections.
Job Requirements:
Bachelor's degree or above, with over 5 years of experience in time series approval;
Familiar with timing analysis of advanced process nodes, with relevant chip production experience preferred;
Proficient in using mainstream STA (Static Timing analysis) tools such as PrimeTime and proficient in scripting languages such as Tcl/Perl/Python;
Proficient in temporal analysis methods, able to quickly locate and independently solve temporal problems;
Can optimize the STA process to ensure the efficiency and accuracy of timing analysis.
