Senior Physical Design Engineer (PnR)

We are seeking a Senior Physical Design Engineer with 8+ years of experience in ASIC/SoC implementation. The ideal candidate will have strong expertise in full-chip and block-level Physical Design, including Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, Timing Closure, and Physical Signoff for advanced technology nodes.

Key Responsibilities

• Perform end-to-end Physical Design implementation from netlist to GDSII.
• Drive Floorplanning, Power Planning, Placement, CTS, Routing, and Physical Verification.
• Analyze and close timing, congestion, power, signal integrity, and DRC/LVS issues.
• Collaborate with RTL, DFT, STA, and Verification teams to achieve design closure.
• Optimize area, power, and performance (PPA) targets.
• Support tapeout activities and silicon bring-up.

Required Qualifications

• Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering.
• 8+ years of hands-on experience in ASIC/SoC Physical Design.
• Strong expertise in: Floorplanning, Power Planning, Placement & Optimization, CTS and Timing Closure, Routing and Physical Verification, IR Drop, EM, and Signal Integrity analysis
• Experience with industry-standard EDA tools such as: Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, Calibre
• Strong understanding of advanced technology nodes (16nm and below preferred).
• Proficiency in Tcl, Perl, or Python scripting.

Preferred Qualifications

• Experience with full-chip integration and tapeout.
• Knowledge of low-power design methodologies (UPF/CPF).
• Exposure to AI/HPC, Networking, Mobile, or Automotive SoCs.
• Experience in advanced nodes such as 7nm, 5nm, or below.

Key Skills

• Excellent timing and physical closure debugging skills.
• Strong analytical and problem-solving abilities.
• Effective communication and cross-functional collaboration.
• Ability to mentor junior engineers and drive project deliverables independently.