Senior Staff Design Verification Engineer (DV)

Our client is a cutting-edge semiconductor solutions provider specializing in advanced SoC, chiplet, and multi-die technologies. With a focus on high-performance, low-power, and scalable designs, they are driving next-generation innovations that power data centers, AI, automotive, and consumer applications worldwide.

Job Summary

This role will lead the DV team through all project phasesfrom planning to execution. The incumbent will have strong technical background while leading the team. The responsibilities cover verifying the functional correctness, performance, and robustness of the design.

Key Responsibilities

Develop and execute comprehensive pre-silicon validation test plans

Create UVM/RTL-based testbenches

Perform simulation, code coverage analysis, and debug failures using tools such as VCS, Questa, or Xcelium.

Support assertion-based verification, formal verification, or hybrid methods where applicable.

Required Experience

Bachelor or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

At least 8 years of experience in SoC/NoC design validation, preferably in a product environment.

Experience in SystemVerilog, UVM, scripting (Python/Perl/TCL), and simulation tools.

Strong debugging and problem-solving skills in a multi-disciplinary team.