Leading the design, implementation, and integration of complex digital blocks and IPs into SoCs, focusing on high-quality Verilog/SystemVerilog, PPA(Power,Performance,Area) and ensuring seamless cross-functional collaboration (PD, DV, Firmware) for first-time silicon success, mentoring junior engineers, and driving new methodologies.
Job Responsibilities
- SOC Integration: Lead integration of major subsystems (PCIe, CXL, NoC) and IP blocks, resolving inter-IP issues.
- Verification & Quality:Drive rigorous RTL quality checks (Lint, CDC, Formal), simulation, and support DV teams.
- Optimization:Optimize designs for Power, Performance, and Area (PPA) targets, experience low-power techniques (UPF) is a plus.
- Front-End Flow Ownership:Drive Lint, CDC, Synthesis, DFT, RDC, and Formality checks, often scripting automation (Python) and resolving issues.
- Cross-Functional Leadership:Collaborate with Verification, Physical Design, Firmware, and Validation teams, bridging gaps and resolving complex integration challenges.
- Mentorship & Methodology:Mentor junior engineers, conduct design reviews, and introduce new tools/best practices to improve efficiency.
Job Skills & Experience
- Languages:Expert Verilog/SystemVerilog.
- Tools:RTL Linting (Meridian, SpyGlass), CDC tools, Simulation (Questa, VCS), Synthesis (Design Compiler), Formal Verification.
- Concepts:Clock Domain Crossing (CDC), Design for Test (DFT), Static Timing Analysis (STA), Power Management (UPF) is a plus.
- Protocols:Experience with AXI, AHB, PCIe, NoC, CHI is a plus.
- Leadership:Proven ability to lead technical efforts, drive projects, and mentor teams.
- Experience:Bachelor's/Master's degree in EE/CS with >9+ years of relevant ASIC/SOC integration experience, deep understanding of SOC architecture.
