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Sr Principal Design Engineer

CADENCE
12-14 Years
Bengaluru, India
  • Posted 2 months ago
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Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

12-14 yrs of work experiences in VLSI domain with Master's/bachelor's degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim debug skills Should be able to manage project schedule and delivery independently

Should be good in Perl/Tcl scripting and automation

We're doing work that matters. Help us solve what others can't.

More Info

Job Type:
Permanent Job
Industry:
Other
Function:
Vlsi
Employment Type:
Full time

About Company

Job ID: 148297443

Last Updated: 10-08-2026 07:26:39 PM
Homejobs in Bengaluru / BangaloreSr Principal Design Engineer

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Sr Principal Design Engineer

CADENCE
Bengaluru, India

Skills:

Debugging, Test architecture definition, Low power CLP checks, LEC checks, Zero delay and timing simulations, RTL changes for DFT, Boundary scan ACJTAG IEEE 1500 implementation and verification, DFT ownership, Scan and ATPG for different fault models, Timing constraints for test mode timing closure, Scan Insertion, Post silicon bring up, IEEE1687 iJTAG compliant ICL PDL for functional manufacturing tests

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