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3-5 Years
Not Disclosed
  • Posted 16 hours ago
  • Be among the first 10 applicants

Job Description

WE ARE HIRING – STA ENGINEERS

Role: Static Timing Analysis (STA) Engineer

Experience: 3+ Years

Location: malaysia (Penang)

Notice Period: Immediate to 30 Days

Key Responsibilities:

• Perform Static Timing Analysis (STA) for complex SoC designs

• Timing constraints development, validation, and debugging

• Analyze setup/hold violations and perform timing closure

• Work on SDC constraints, clocks, IO delays, false paths, multicycle paths, etc.

• Timing ECO implementation and optimization

• Collaborate with RTL, PD, CTS, and Signoff teams

• Perform MCMM timing analysis and signoff

• Debug timing issues across different PVT corners

• Generate and analyze timing reports

Required Skills:

• Strong knowledge of STA concepts and timing closure

• Hands-on experience with PrimeTime or equivalent STA tools

• Good understanding of SDC, STA, CTS, and PVT corners

• Experience with MCMM analysis and timing ECOs

• Good understanding of ASIC physical design flow

• Strong debugging and problem-solving skills

Interested candidates can share their updated resume at:

[Confidential Information]

#Hiring #STA #StaticTimingAnalysis #ASIC #VLSI #Semiconductor #TimingClosure #PrimeTime #PhysicalDesign #BangaloreJobs #NoidaJobs #VLSIJobs #SemiconductorJobs

More Info

Job Type:
Function:
Employment Type:

Key Skills

MCMM analysis

CTS

Timing ECOs

PVT corners

ASIC physical design flow

Static Timing Analysis (STA)

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3-5 yrs
Penang, Malaysia
Skills:
clock-domain crossing (CDC) analysis, Static Timing Analysis (STA), formal verification, RTL synthesis, LINT, Verilog RTL design, Timing Analysis, formal equivalence checking, timing constraint validation, Unix/Linux environments