STA Engineer

Responsibilities:

• Has done timing sign-off including timing margin calculations independently on SOC level.
• Experience in handling STA of multi-power domain designs
• STA flow enhancement, abstraction with bottleneck identification.
• Proficient in design margins and SDC constructs
• TAT reduction in multi-mode, multi power domain/designs.
• Generate timing ECOs for Physical Design
• Drive ambitious schedules and enables dependent teams to accomplish

Requirements:

• Proficient with EDA tools from Synopsys/ Cadence
• Excellent analytical & communication skill
• Show ability to collaborate in multi-functional environment, cross-site or cross-time zone
• Proficient in Tcl and Perl or other scripting relevant language is a plus
• Strong in STA fundamentals
• Bachelor's or Master's degree in Electrical/Electronic Engineering or a related field.
• 3 - 10 years of relevant experience