Staff Engineer
- Posted 2 months ago
- Be among the first 10 applicants
Job Description
Looking for an experienced senior verification engineer with 8-10 years of experience in ASIC/SOC/IP/block level functional verification using system verilog/UVM.
The ideal candidate will have strong command of UVM, advanced UVM and system verilog
Key responsibilities:
The ideal candidate will have strong command of UVM, advanced UVM and system verilog
Key responsibilities:
- Develop a comprehensive test plan, complete test-bench and robust verification environment including interface agents and scoreboard in UVM.
- Possess deep knowledge of at least one industry-standard protocol such as Ethernet, PCIe, DDR, USB.
- Strong debugging skills to address TB issues quickly and test failures.
- Take responsibility for verification closure by addressing coverage and managing bug reports.
- Proficiency in using industry standard verification tools such as Questa, VCS or ModelSim.
- Experience with scripting languages like python, perl or TCL for automation tasks.
- Able to track & manage Daily and weekly progress and manage a team of 6 to 7 Engineers.
- Interact with the customer on the tasks and status updates.
More Info
About Company
Skills:
PCS, Ovm, Hdl Languages, Shell, Perl, Verilog, Python, System Verilog, Tcl, assertion-based verification methodologies, PHY, Ethernet standard packet-based verification, Uvm, Ethernet MAC, VHDL, directed simulation testcases
Skills:
Object-Oriented Programming (OOP) concepts, Design Patterns, Data structures, Log Analysis, Algorithms, Linux Internals, Restful Apis, Python, System telemetry, Messaging queues, Database layer optimization, CI/CD automation, Production debugging, Java Spring Spring Boot, Microservices design, Distributed Systems Architecture, Integration testing frameworks
Skills:
boundary scan , Jtag, Perl, Python, Tcl, LINT, ASIC design flow, DFT DRC, cdc, Analog DFT, MBIST, Scan compression, Scan stitching, Dft, Low power DFT Techniques, ATPG, Low Power Checks, RTL Coding, ATPG Coverage improvement, LBIST, DFT STA Constraint development, Siemen’s DFT EDA tools
Skills:
PERL, Python, Tcl, Fusion Compiler, Cadence, UPF, Place Route, Innovus, formal verification, Physical Design, Power-Plan, Floorplan, Synopsys
Skills:
PowerShell, Python, SOTI MobiControl, HP Thin Clients, Enterprise MDM