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Staff Engineer- DV
Job Description
Key Responsibilities
- Implement modular UVM testbenches at the MCU level for SoC subsystems such as sensor hubs, AI accelerators, and communication fabrics
- Develop comprehensive coverage-driven verification plans covering functional, code, and assertion coverage aligned with automotive safety and security standards
- Debug complex SoC-level scenarios including multi-protocol interactions and power-aware verification
- Integrate and customize third-party Verification IPs (VIPs) like Synopsys, Cadence, and Mentor for automotive protocols
- Provide technical leadership and ownership of design verification tasks
- Communicate clearly and transparently within the team and with global customers
- Adapt to agile project requirements and changing timelines
- Contribute innovative ideas to improve design quality and verification workflows
More Info
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About Company
Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier.As the industrys leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog Connectivity, and Power.
Skills:
System Verilog, CPU Core Verification, Uvm, Coverage models, Constrained-random tests, Scoreboards, Checkers, Testbenches