STAFF ENGINEER, PKG SI INT

As a Staff Engineer, Package-Silicon Integration in Micron's Package Development Engineering (PDE) organization, you will drive package-silicon integration for next-generation NAND packaging technologies.

You will collaborate across silicon design, wafer fabrication, package design, assembly, reliability, and manufacturing to identify and mitigate chip-package interaction risks. You will independently lead complex technical workstreams, develop integration solutions, and leverage AI-enabled and data-driven methods to accelerate engineering learning and enable robust design and manufacturing solutions.

Key Responsibilities

• Lead Chip-Package Interaction (CPI) risk assessments for new silicon, package architectures, materials, and processes.

• Partner with silicon, package, wafer fab, and assembly teams to resolve dicing, singulation, die integrity, and integration challenges.

• Lead technical investigations using DOE, statistical analysis, physical characterization, failure analysis, reliability data, and AI-enabled analytical approaches where appropriate.

• Drive root-cause analysis and solutions for yield, quality, reliability, and manufacturability issues.

• Define and execute test vehicles, characterization strategies, process windows, and qualification plans.

• Translate technical learning into design rules, specifications, FMEA controls, and Best-Known Methods (BKMs).

• Leverage AI, automation, and data analytics to improve engineering efficiency, technical insight, knowledge capture, and decision-making.

• Drive technology readiness and transition of new silicon and package technologies into manufacturing.

• Identify integration and capability gaps and develop scalable technical solutions.

• Communicate technical risks, findings, and recommendations across engineering teams and leadership.

• Provide technical guidance and mentoring while promoting effective AI-enabled ways of working.

Minimum Qualifications

Education & Experience

• Bachelor's degree or higher in Mechanical, Materials, Electrical/Electronic, Chemical, Semiconductor Engineering, Physics, or a related technical discipline.

• Min 4 to 5 years of relevant semiconductor experience in either package-silicon integration, advanced packaging, wafer technology, assembly, reliability, materials, or process development.

• Demonstrated ability to independently lead complex technical investigations.

Technical & Professional Skills

• Strong understanding of semiconductor fabrication, packaging, assembly, materials, and/or reliability.

• Experience in areas such as CPI, wafer/die mechanics, dicing, die integrity, package assembly, characterization, failure analysis, or reliability.

• Experience with DOE, statistical analysis, root-cause analysis, DFMEA/PFMEA, and structured problem solving.

• Ability to connect physical failure mechanisms to silicon, package, material, and process interactions.

• Ability to translate technical findings into design requirements, process specifications, and manufacturing controls.

• Proficiency in using data analytics, automation, and AI-enabled tools to improve engineering analysis, productivity, technical documentation, and problem solving.

• Ability to critically assess AI-generated outputs and apply engineering judgment and data validation before using them for technical decisions.

• Strong cross-functional collaboration, technical leadership, and communication skills.