Are you ready to drive tapeout success on the most advanced silicon nodes in the world We are looking for an experienced Staff/Senior Staff Physical Design Engineer to co-lead our RTL-to-GDSII team and push the boundaries of PPA on deep sub-micron nodes (7nm and below).
Working directly alongside our Physical Design Leadership, you will serve as the core technical authority—shaping implementation strategies, mentoring talented engineers, and executing on complex, high-stakes tapeouts.
If you wish to explore into people management, we are open to offer managerial-based job position tally with your years of experience.
We highly value candidates with flexibility of technical leadership and people management.
Responsibilities:
- Technical Co-Leadership: Work closely with PD Management (manager/senior manager) to guide and inspire the team, steering projects toward tapeout convergence.
- Silicon Architecture & Execution: Drive floorplanning, placement strategy, CTS optimization, and full-chip physical integration tailored to tight PPA targets.
- Low-Power Mastery: Architect and execute complex low-power design strategies across multiple power domains (UPF/CPF, power gating, clock-gating).
- Signoff & Convergence: Work on multi-corner Static Timing Analysis (STA), physical verification (PV), and vector-based power analysis through to final signoff.
- Cross-Functional Collaboration: Partner with front-end, DFT, and CAD leads to streamline execution and achieve towards tapeout with targeted audit checklists.
- Fast-pace adaptation to different work environments: ability to switch and adapt quickly to different project and EDA tools.
Preferred Experience:
- Advanced Node Experience: 7-10+ years in silicon physical design, implementation, or signoff methodology on sub-7nm process technologies.
- Specialized Expertise: Deep hands-on strength in either RTL-to-Netlist (Synthesis) or Netlist-to-GDSII (P&R). (Full-flow RTL2GDS experience is a huge plus!)
- EDA Tool: Proven proficiency with EDA design & verification tools:
Synopsys: Fusion Compiler, Design Compiler, ICC2, PrimeTime, StarRC
Cadence / Mentor / Ansys: Genus, Innovus, Tempus, Pegasus, Calibre, RedHawk
- Automation & Scripting: Strong Unix foundation with fluency in TCL, Python, Shell, or Perl, along with a solid understanding of Verilog/VHDL.
- Leadership & Influence: Outstanding communication skills with the confidence to drive client-facing technical discussions and align with project management.
Bonus Points:
- Experience with High-Speed SerDes integration at the block, subsystem, or full-chip level.
- Familiarity or hands-on exposure with AI-agent-assisted design environments.
Why Join Us
If you thrive on tackling complex multi-million gate challenges, mastering cutting-edge toolchains, and leading engineering teams to victory at signoff, we want to hear from you.
