Job Details
Job Description:
The Test Architect Engineer is responsible for defining and integrating advanced test architectures and methodologies to support end-to-end post-silicon engineering activities. This role ensures robust, scalable, and reusable test solutions that enable efficient validation, characterization, and high-volume manufacturing readiness for complex analog and RF components.
Key Responsibilities
Test Architecture & Strategy
- Own the test program architecture: modular test flow design, instrument resource planning, and reuse strategy across product families.
- Translate product requirements and datasheet specs into testable requirements and acceptance criteria (accuracy, linearity, noise, drift, timing).
- Define test coverage for parametric, functional, reliability and DFT/BIST hooks for analog blocks (ADC/DAC, LDOs, PLLs, RF).
Development & Implementation
- Develop analog measurement routines with calibration, de-embedding, and guardbanding.
- Build test fixtures and loadboard requirements in collaboration with HW teams; specify analog signal integrity, probe/handler constraints, socket/thermal solutions
- Create golden device workflows, correlation scripts, and reference calibration procedures.
Characterization, Correlation & Quality
- Define silicon bring-up and characterization plans (corners, voltage/temperature, stress); perform DOE/Hypothesis-driven analysis to isolate systemic issues.
- Drive lab-to-ATE correlation (bench tester), methodically quantify measurement uncertainty (bias, repeatability, reproducibility).
Yield, Cost & Efficiency
- Reduce test time and cost via multi-site enablement, efficient resource scheduling, instrument sharing, concurrency, and algorithmic optimizations.
- Partner with manufacturing to improve OEE, execution goal rate, and first-pass yield; define test escape prevention methodologies.
- Define test solutions to be productize in HVM to meet best-in-class PHI.
Qualifications
- BS/MS in Electrical Engineering (PhD a plus) with 1-2 years in analog/mixed-signal test development for semiconductors.
- Hands-on with ATE platforms: Advantest V93000 (SmarTest); strong understanding of instrumentation (SMU, AWG, digitizers, RF).
- Proficient in C/C++/C#/Python/TCL for test program development; familiarity with CI/CD, version control (Git), and build systems.
- Deep knowledge of analog measurement principles: calibration, de embedding, error budgeting, linearity, noise, stability, timing/jitter.
- Strong data analysis skills (SPC, DOE, regression, outlier detection) and problem-solving using FMEA/Hypothesis testing.
- Experience with DFT/BIST hooks for analog blocks, DFM/DPF considerations, and handler/prober/fixture constraints.
Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to our staffing team at [Confidential Information].
Job Type
Experienced Hire
Shift
Shift 1 (Malaysia)
Primary Location:
Malaysia, Penang
Additional Locations:
Business Group
The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
